Static random access memory (SRAM) is an essential component in most computer processor based systems. SRAM chips typically include millions of individual cells, each for storing a single digital bit value.
Conventional wisdom has heretofore dictated the use of differential circuit techniques for SRAM cell implementations. Single-ended storage cell designs have not heretofore been able to provide the needed cell stability during read operations while at the same time providing fast enough write capability. The problem arises due to the competing design requirements when reading a logic low value (i.e., a "0") from a storage cell and writing a logic high value (i.e., a "1") to the same cell. Design requirements for ease in reading a "0" from a cell are generally the opposite of design requirements for writing a "1" to the same cell. Differential storage cell designs overcome these design issues by balancing the storage cell inverters and providing dual I/O access to the cell. However, differential storage cell designs require twice as many bitlines and an additional access transistor as compared to single-ended storage cell designs. Accordingly, a need exists for a single-ended storage cell design that provides stability during read operations and speed during write operations.